LAN9353 Datasheet, PDF (93/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
8.3.3 INTERRUPT ENABLE REGISTER (INT_EN)
Offset:
05Ch
Size:
32 bits
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding
interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the
interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of Soft-
ware Interrupt Enable (SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS)
bits, which mimic the layout of this register.
Bits
31
30
29
28
27
26
25:23
22
21:20
19
18
17
16:13
12
11:3
2:1
0
Description
Software Interrupt Enable (SW_INT_EN)
Device Ready Enable (READY_EN)
1588 Interrupt Event Enable (1588_EVNT_EN)
Switch Engine Interrupt Event Enable (SWITCH_INT_EN)
Physical PHY B Interrupt Event Enable (PHY_INT_B_EN)
Physical PHY A Interrupt Event Enable (PHY_INT_A_EN)
RESERVED
RESERVED
RESERVED
GP Timer Interrupt Enable (GPT_INT_EN)
RESERVED
Power Management Event Interrupt Enable (PME_INT_EN)
RESERVED
GPIO Interrupt Event Enable (GPIO_EN)
RESERVED
RESERVED
RESERVED
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
R/W
RO
R/W
RO
R/W
RO
RO
RO
Default
0b
0b
0b
0b
0b
0b
-
-
-
0b
-
0b
-
0b
-
-
-
 2015 Microchip Technology Inc.
DS00001925A-page 93