LAN9353 Datasheet, PDF (388/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.4.1.2 Port 0 MAC Mode SMI Managed - Device Initialization
In this mode, during device initialization, Physical PHYs A and B are accessed by the PMI. The SMI slave block is
accessed via an external master attached to the Port 0 MII/RMII pins. The Virtual PHY 0 parallel interface is accessible
via the EEPROM Loader. However, this block is not used in this mode. The PMI parallel interface is accessible via the
EEPROM Loader. The EEPROM Loader may access PHYs A and B through the PMI registers.
Figure 14-4 details the MII Mode Multiplexer management path connections for this mode.
FIGURE 14-4:
MII MUX MANAGEMENT PATH CONNECTIONS - MAC MODE SMI MANAGED -
DEVICE INITIALIZATION
mdi SMI Slave
mdo
mdc
Parallel
Master
mdio_dir
mdi Virtual PHY 0
mdo
mdc
Parallel
Slave
mdio_dir
mdi PHY B
mdo
mdio_dir
mdc
mdi PHY A
mdo
mdio_dir
mdc
Management
Mode Selection
MII Pins
mdio_dir
p
mdo
i
n
mdi
m
mdc_dir
u
x
mdc_out
i
n
mdc_in
g
P0_MDIO
P0_MDC
Management
Mode Selection
mdo mdc mdi mdio_en_n
PMI
Parallel Slave
DS00001925A-page 388
 2015 Microchip Technology Inc.