LAN9353 Datasheet, PDF (201/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
Type
9:8 Mode[1:0]
RO
This field combined with Mode[2] indicates the operating mode of the port.
000: MII MAC mode
001: MII PHY mode
010: RMII MAC mode
011: RMII PHY mode
100: Reserved (Port 0) / Internal PHY (Port 1)
Note:
When operating in RMII modes, the drive strength of the RMII
output clock is selected using the RMII/Turbo MII Clock Strength
bit.
7
Switch Collision Test
R/W
When set, the collision signal to the switch fabric is active during transmis-
sion from the switch engine.
Note: It is recommended that this bit be used only when using loopback
mode.
6
RMII Clock Direction
0: Selects Px_REFCLK as an Input
1: Selects Px_REFCLK as an Output
R/W
NASR
Note 70
5
RMII/Turbo MII Clock Strength
R/W
For RMII MAC and PHY modes and 200 Mbps MII PHY mode, a low selects
12 mA drive while a high selects a 16 mA drive. For 100 Mbps and 10 Mbps
MII PHY modes, the drive strength is fixed at 12mA.
NASR
Note 70
4:2 Current Speed/Duplex Indication
RO
This field indicates the current speed and duplex of the Virtual PHY link.
[4]
[3]
[2]
Speed
Duplex
0
0
0
0
0
1
RESERVED
10Mbps
half-duplex
0
1
0
100/200Mbps
half-duplex
0
1
1
1
0
0
RESERVED
RESERVED
1
0
1
10Mbps
full-duplex
1
1
0
100/200Mbps
full-duplex
1
1
1
RESERVED
1
RESERVED
RO
Default
Note 65
0b
Note 67
Note 68
Note 69
-
0
SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
R/W
NASR
Note 70
This bit is used only in MII PHY mode. It is not used in RMII PHY or MII / RMII
MAC modes.
Note 71
Note 64: The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD bound-
ary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Note 65: The default value of this field is determined via the P0_mode_strap[1:0] or P1_mode_strap[2:0] configura-
tion straps. Refer to Section 7.2, "Hard-Straps," on page 78 for additional information.
 2015 Microchip Technology Inc.
DS00001925A-page 201