LAN9353 Datasheet, PDF (347/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 12-1: I²C MASTER TIMING VALUES (CONTINUED)
Symbol
Description
Min
Typ
Max
Units
t_hd;dat;out
t_su;sto
t_buf
t_sp
Hold time (provided to slave) of EESDA output after
EESCL falling
Setup time (provided to slave) of EESCL high
before EESDA output rising for stop condition
Bus free time
Input spike suppression on EESCL and EESDA
1000
Note 3
4.5
Note 1
4.7
ns
s
s
100
ns
Note 1: These values provide 500 ns of margin compared to the I²C specification.
Note 2: This value provides 50 ns of margin compared to the I²C specification.
Note 3: These values provide 1000 ns of margin compared to the I²C specification.
Based on the eeprom_size_strap configuration strap, various sized I²C EEPROMs are supported. The varying size
ranges are supported by additional bits in the EEPROM Controller Address (EPC_ADDRESS) field of the EEPROM
Command Register (E2P_CMD). Within each size range, the largest EEPROM uses all the address bits, while the
smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM controller drives all the address bits as
requested regardless of the actual size of the EEPROM. The supported size ranges for I²C operation are shown in
Table 12-2.
TABLE 12-2: I²C EEPROM SIZE RANGES
eeprom_size_strap
0
1
# of Address Bytes
1 (Note 4)
2
EEPROM Size
EEPROM Types
128 x 8 through 2048 x 8
24xx01, 24xx02, 24xx04,
24xx08, 24xx16
4096 x 8 through 65536 x 8 24xx32, 24xx64, 24xx128,
24xx256, 24xx512
Note 4: Bits in the control byte are used as the upper address bits.
12.3.1 I²C EEPROM DEVICE ADDRESSING
The I²C EEPROM is addressed for a read or write operation by first sending a control byte followed by the address byte
or bytes. The control byte is preceded by a start condition. The control byte and address byte(s) are each acknowledged
by the EEPROM slave. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted (a start con-
dition and a stop condition are sent) and the EEPROM Controller Timeout (EPC_TIMEOUT) bit of the EEPROM Com-
mand Register (E2P_CMD) is set.
The control byte consists of a 4 bit control code, 3 bits of chip/block select and one direction bit. The control code is
1010b. For single byte addressing EEPROMs, the chip/block select bits are used for address bits 10, 9 and 8. For double
byte addressing EEPROMs, the chip/block select bits are set low. The direction bit is set low to indicate the address is
being written.
 2015 Microchip Technology Inc.
DS00001925A-page 347