LAN9353 Datasheet, PDF (380/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
SMI READ POLLING FOR INITIALIZATION COMPLETE
Before device initialization or during power management, the SMI slave interface will not return valid data. To determine
when the SMI slave is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern
is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Con-
figuration Register (HW_CFG) can be polled to determine when the device is fully configured.
Device initialization may finish, or power management may exit, between the two 16-bit halves of a DWORD access,
therefore the device may not see both WORD accesses. However, the device cannot be left in a state where it expects
another 16-bit read to complete the DWORD cycle. Specific registers may be read during a reset without leaving the
device in such a state. These are the Byte Order Test Register (BYTE_TEST), the Hardware Configuration Register
(HW_CFG), the Power Management Control Register (PMT_CTRL) and the Reset Control Register (RESET_CTL).
14.2.3.2 Write Sequence
In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY Address, 5-bit
Register Address, 2-bit turn-around time and finally the 16 bits of data. The MDIO pin is three-stated throughout the
write sequence.
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. No order-
ing requirement exists. The host may access either the low or high WORD first, as long as the next write is performed
to the opposite WORD. It is assumed that the second write is to the same register and opposite WORD. There is no
hardware check.
Note: The host must not perform SMI writes to unused register addresses. There is no hardware check.
DS00001925A-page 380
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