LAN9353 Datasheet, PDF (38/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
4.0 POWER CONNECTIONS
Figure 4-1 and Figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec-
tively. Refer to the device reference schematic and the device LANCheck schematic checklist for additional information.
Section 4.1 provides additional information on the devices internal voltage regulators.
FIGURE 4-1:
POWER CONNECTIONS - REGULATORS ENABLED
+1.8 V to
+3.3 V
+3.3 V
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
+3.3 V
VDD33
REG_EN
To PHY1
Magnetics
(or separate 2.5V)
To PHY2
Magnetics
(or separate 2.5V)
VDD33TXRX1
VDD33BIAS
VDD33TXRX2
VSS
(exposed pad)
IO Pads
Core Logic &
PHY digital
Internal 1.2 V Core
+3.3 V ^Regulator +1.2 V
(IN)
(OUT)
enable
Internal 1.2 V Oscillator
+3.3 V ^Regulator +1.2 V
(IN)
(OUT)
enable _VSS
Crystal Oscillator
VSS
Ethernet PHY 1
Analog
Ethernet Master
Bias
Ethernet PHY 2
Analog
PLL
VDDCR
VDDCR
VDDCR
(Pin 6)
OSCVDD12
470 pF
1.0 µF
0.1  ESR
OSCVSS
VDD12TX1
VDD12TX2
Note: Bypass and bulk caps as needed for PCB
DS00001925A-page 38
 2015 Microchip Technology Inc.