LAN9353 Datasheet, PDF (196/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.6
Port x Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY_x)
Offset:
PORT0: 1D4h
PORT1: 0D4h
Index (decimal): 5
Size:
32 bits
16 bits
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-Negotiation pro-
cess with the Virtual PHY. Because the Virtual PHY does not physically connect to an actual link partner, the values in
this register are emulated as described below.
Bits
Description
31:16 RESERVED
(See Note 55)
15 Next Page
This bit indicates the emulated link partner PHY next page capability and is
always 0.
0: Link partner PHY does not advertise next page capability
1: Link partner PHY advertises next page capability
14 Acknowledge
This bit indicates whether the link code word has been received from the
partner and is always 1.
0: Link code word not yet received from partner
1: Link code word received from partner
13 Remote Fault
Since there is no physical link partner, this bit is not used and is always
returned as 0.
12 RESERVED
11 Asymmetric Pause
This bit indicates the emulated link partner PHY asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner
1: Asymmetric PAUSE toward link partner
10 Pause
This bit indicates the emulated link partner PHY symmetric pause capability.
0: No Symmetric PAUSE toward link partner
1: Symmetric PAUSE toward link partner
9
100BASE-T4
This bit indicates the emulated link partner PHY 100BASE-T4 capability. This
bit is always 0.
0: 100BASE-T4 ability not supported
1: 100BASE-T4 ability supported
Type
RO
RO
RO
RO
RO
RO
RO
RO
Default
-
0b
Note 56
1b
Note 56
0b
Note 56
-
Note 57
Note 57
0b
Note 56
DS00001925A-page 196
 2015 Microchip Technology Inc.