LAN9353 Datasheet, PDF (401/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
(1588_RX_TS_INSERT_CONFIG_x).
Note: For version 2 of IEEE 1588, the four reserved bytes starting at offset 16 should be used for the nanosec-
onds. The reserved byte at offset 5 should be used for the seconds.
DELAY REQUEST EGRESS TIME INSERTION INTO DELAY REPONSE PACKET
Normally, in ordinary clock operation, the egress times of transmitted Delay_Req packets are saved and read by the
Host S/W. To avoid the need to read these timestamps via register access, the egress time of the last transmitted
Delay_Req packet on the port can be inserted into Delay_Resp packets received on the port.
This function is enabled via the RX PTP Insert Delay Request Egress in Delay Response Enable (RX_PT-
P_INSERT_DREQ_DRESP_EN) bit in the 1588 Port x RX Timestamp Insertion Configuration Register (1588_RX-
_TS_INSERT_CONFIG_x).
As with any Ingress Time Insertion, Delay_Resp messages must be enable in the 1588 Port x RX Timestamp Configu-
ration Register (1588_RX_TIMESTAMP_CONFIG_x) and the RX PTP Insert Timestamp Enable (RX_PT-
P_INSERT_TS_EN) must be set.
Note: Inserting the delay request egress time into the packet is an additional, separately enabled, feature verses
the Egress Time Recording described above.
As with INGRESS TIME INSERTION INTO PACKETS, above:
• The versionPTP field of the PTP header is checked and the domainNumber field and alternateMasterFlag in the
flagField of the PTP header are not checked.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
• The four bytes of nanoseconds / 2 bits of seconds are stored at the specified offset of the PTP header.
• Bits 3:0 of the seconds are stored at the specified offset in the PTP header, if enabled.
Effectively, this function is the same as the INGRESS TIME INSERTION INTO PACKETS except that the egress time
of the Delay_Req is inserted instead of the ingress time of the Delay_Resp.
INGRESS CORRECTION FIELD RESIDENCE TIME ADJUSTMENT
In order to support one-step transparent clock operation, the residence time delay through the device is accounted for
by adjusting the correctionField of certain packets.
This function is enabled per PTP message type via the RX PTP Correction Field Message Type Enable (RX_PT-
P_CF_MSG_EN[15:0]) bits in the 1588 Port x RX Correction Field Modification Register (1588_RX_CF_MOD_x). Typ-
ically the Sync message is enabled for both end-to-end and peer-to-peer transparent clocks, the Delay_Req,
PDelay_Req and PDelay_Resp messages are enabled only for end-to-end transparent clocks.
Following the determination of packet format and qualification of the packet as a PTP message above, the PTP header
is checked.
• The versionPTP field of the PTP header is checked against the RX PTP Version (RX_PTP_VERSION[3:0]) field in
the 1588 Port x RX Timestamp Configuration Register (1588_RX_TIMESTAMP_CONFIG_x). Only those mes-
sages with a matching version will be have their correction field modified. A setting of 0 allows any PTP version.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
Note: The domainNumber field and alternateMasterFlag in the flagField of the PTP header are not tested for pur-
pose of correction field modification.
The correctionField is modified as follows:
Note: If the original correctionField contains a value of 0x7FFFFFFFFFFFFFFF, it is not modified.
If adjustment to the correctionField would result in a value that is larger than 0x7FFFFFFFFFFFFFFF, that
value is used instead.
• For Sync packets, the value of the RX Peer Delay (RX_PEER_DELAY[15:0]) field in the 1588 Port x Asymmetry
and Peer Delay Register (1588_ASYM_PEERDLY_x) (for the particular ingress port) is added to the correction-
Field.
This function is used for one-step peer-to-peer transparent clocks. If peer-to-peer transparent clock mode is not
being used, the register should be set to zero. If one-step transparent clock mode is not being used, correction
field modifications would not be enabled for Sync messages.
 2015 Microchip Technology Inc.
DS00001925A-page 401