LAN9353 Datasheet, PDF (31/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-7: SWITCH PORT 1 RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
Buffer
Type
VIS/
VO12/
VO16
(PD)
Note 9
Description
RMII MAC Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P1_IND[1:0], P1_INDV, P1_OUTD[1:0],
and P1_OUTDV pins. The choice of input verses
output is based on the setting of the RMII Clock
Direction bit in the Port 1 Port x Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CON-
TROL_STATUS_x). A low selects P1_OUTCLK as
an input and a high selects P1_OUTCLK as an out-
put.
As an input, the pull-down is enabled by default.
Port 1 RMII
Reference Clock
1
P1_REFCLK
VIS/
VO12/
VO16
(PD)
Note 9
As an output, the input buffer and pull-down are dis-
abled. The choice of drive strength is based on the
MII Virtual PHY RMII/Turbo MII Clock Strength bit. A
low selects a 12 mA drive, while a high selects a
16 mA drive.
RMII PHY Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P1_IND[1:0], P1_INDV, P1_OUTD[1:0],
and P1_OUTDV pins. The choice of input verses
output is based on the setting of the RMII Clock
Direction bit in the Port 1 Port x Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CON-
TROL_STATUS_x). A low selects P1_OUTCLK as
an input and a high selects P1_OUTCLK as an out-
put.
As an input, the pull-down is normally enabled. The
input buffer and pull-down are disabled when the
Isolate (VPHY_ISO) bit is set in the Port 1 Port x Vir-
tual PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
As an output, the input buffer and pull-down are dis-
abled. The choice of drive strength is based on the
MII Virtual PHY RMII/Turbo MII Clock Strength bit. A
low selects a 12 mA drive, while a high selects a
16 mA drive. The output driver is disabled when the
Isolate (VPHY_ISO) bit is set in the Port 1 Port x Vir-
tual PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
(PD) Internal PHY Mode: This pin is not used.
Port 1 Mode[0]
Configuration
Strap
P1_MODE0
VIS
(PU)
Note 11
This strap configures the mode for Port 1. See
Note 10.
Refer to Table 7-4, “Port 1 Mode Strap Mapping,” on
page 83 for the Port 1 strap settings.
Note 9: A series terminating resistor is recommended for the best PCB signal integrity.
Note 10: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 67
for more information.
 2015 Microchip Technology Inc.
DS00001925A-page 31