LAN9353 Datasheet, PDF (21/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
1
Port 0 MII/RMII
Input Data 0
P0_IND0
1
Port 0 MII/RMII
Input Data Valid
P0_INDV
1
Port 0 MII/RMII
Input Error
P0_INER
Buffer
Type
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
-
Description
MII MAC Mode: This pin is the receive data 0 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 0 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
RMII MAC Mode: This pin is the receive data 0 bit
from the external PHY to the switch.
RMII PHY Mode: This pin is the transmit data 0 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
MII MAC Mode: This pin is the RX_DV signal from
the external PHY and indicates valid data on
P0_IND[3:0] and P0_INER.
MII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P0_IND[3:0] and P0_INER. The pull-down and input
buffer are disabled when the Isolate (VPHY_ISO) bit
is set in the Port 0 Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x).
RMII MAC Mode: This pin is the CRS_DV signal
from the external PHY.
RMII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P0_IND[1:0]. The pull-down and input buffer are dis-
abled when the Isolate (VPHY_ISO) bit is set in the
Port 0 Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x).
MII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in the
packet or that Lower Power Idle is being received.
MII PHY Mode: This pin is the TX_ER signal from
the external MAC and indicates that the current
packet should be aborted. The pull-down and input
buffer are disabled when the Isolate (VPHY_ISO) bit
is set in the Port 0 Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x).
RMII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in the
packet.
RMII PHY Mode: This pin is not used.
 2015 Microchip Technology Inc.
DS00001925A-page 21