LAN9353 Datasheet, PDF (486/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
17.3 LED Operation
GPIO[5:0] can be individually selected to function as a LED. These pins are configured as LED outputs by setting the
corresponding LED Enable 5-0 (LED_EN[5:0]) bit in the LED Configuration Register (LED_CFG). When configured as
an LED, the pin is either a push-pull or open-drain / open-source output and the GPIO related input buffer and pull-up
are disabled. The default configuration, including polarity, is determined by input straps or EEPROM entries. Refer to
Section 7.0, "Configuration Straps," on page 67 for additional information.
The functions associated with each LED pin are configurable via the LED Function 2-0 (LED_FUN[2:0]) bits of the LED
Configuration Register (LED_CFG). These bits allow the configuration of each LED pin to indicate various port related
functions. The behaviors of each LED for each LED Function 2-0 (LED_FUN[2:0]) configuration are described in the
following tables. Detailed definitions for each LED indication type are provided in Section 17.3.1 and Section 17.3.2.
The default values of the LED Function 2-0 (LED_FUN[2:0]) and LED Enable 5-0 (LED_EN[5:0]) bits of the LED Con-
figuration Register (LED_CFG) are determined by the LED_fun_strap[2:0] and LED_en_strap[5:0] configuration straps.
For more information on the LED Configuration Register (LED_CFG) and its related straps, refer to Section 17.4.1, "LED
Configuration Register (LED_CFG)," on page 490.
All LED outputs may be disabled by setting the LED Disable (LED_DIS) bit in the Power Management Control Register
(PMT_CTRL). Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive
state.
TABLE 17-1: LED OPERATION AS A FUNCTION OF LED_FUN[2:0] = 000B - 011B
LED5
(GPIO5)
LED4
(GPIO4)
LED3
(GPIO3)
LED2
(GPIO2)
000b
Link / Activity
Port 2
Full-duplex / Collision
Port 2
Speed
Port 2
Link / Activity
Port 1
(if Port 1 internal PHY
enabled)
001b
100Link / Activity
Port 2
Full-duplex / Collision
Port 2
10Link / Activity
Port 2
100Link / Activity
Port 1
(if Port 1 internal PHY
enabled)
Activity
Port 1
(if Port 1 internal PHY
disabled)
Activity
Port 1
(if Port 1 internal PHY
disabled)
010b
TX
Port 0
Link / Activity
Port 2
Speed
Port 2
RX
Port 0
011b
Activity
Port 2
Link
Port 2
Speed
Port 2
Activity
Port 1
DS00001925A-page 486
 2015 Microchip Technology Inc.