LAN9353 Datasheet, PDF (469/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.39 1588 PORT X TX MODIFICATION REGISTER 2 (1588_TX_MOD2_X)
Offset:
Bank:
168h
2
Size:
32 bits
This register is used to configure TX PTP message modifications.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:1 RESERVED
0
TX PTP Clear UDP/IPv4 Checksum Enable
(TX_PTP_CLR_UDPV4_CHKSUM)
This bit enables the clearing of the UDP/IPv4 checksum when Pdelay_Resp
Message Turnaround Time Insertion or Sync Message Egress Time Insertion
is enabled.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
Type
RO
R/W
Default
-
0b
 2015 Microchip Technology Inc.
DS00001925A-page 469