LAN9353 Datasheet, PDF (70/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
Description
Pin / Default Value
speed_strap_1
(cont.)
Port 1 Virtual PHY Speed Select Strap: This strap affects
1b
the default value of the following bits in the (x=1) Port x Virtual
Note: speed_strap_1 and ^{PHY Auto-Negotiation Link Partner Base Page Ability Regis-}
speed_pol_strap_1 share ^{ter (VPHY_AN_LP_BASE_ABILITY_x):}
the same strap register and
EEPROM bit.
• 100BASE-X Full Duplex
• 100BASE-X Half Duplex
• 10BASE-T Full Duplex
• 10BASE-T Half Duplex
Refer to Section 9.3.5.6 and Table 9-23 for more information.
This strap also configures the speed for Port 1 when Virtual
Auto-Negotiation fails. Refer to Section 9.2.6.2, "Parallel
Detection," on page 103 for additional information.
Refer to the respective register definition sections for addi-
tional information.
speed_pol_strap_1
Switch Port 1 Speed Polarity Strap: This strap determines 1b
Note: speed_strap_1 and ^{the polarity of the P1_SPEED pin when in Port 1 RMII MAC}
speed_pol_strap_1 share ^mode.
the same strap register and
EEPROM bit.
0 = P1_SPEED low means 100Mbps, high means 10Mbps
1 = P1_SPEED high means 100Mbps, low means 10Mbps
Refer to the respective register definition sections for addi-
tional information.
duplex_strap_1
PHY A Duplex Select Strap: This strap affects the default
1b
Note: duplex_strap_1 and ^{value of the following register bits (x=A):}
duplex_pol_strap_1 share
the same strap register and ^{• Duplex Mode (PHY_DUPLEX) bit of the PHY x Basic}
EEPROM bit.
Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex bit of the PHY x Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
• PHY Mode (MODE[2:0]) bits of the PHY x Special Modes
Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for addi-
tional information.
DS00001925A-page 70
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