LAN9353 Datasheet, PDF (39/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
FIGURE 4-2:
POWER CONNECTIONS - REGULATORS DISABLED
+1.8 V to
+3.3 V
+3.3 V
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
+3.3 V
VDD33
REG_EN
To PHY1
Magnetics
(or separate 2.5V)
To PHY2
Magnetics
(or separate 2.5V)
VDD33TXRX1
VDD33BIAS
VDD33TXRX2
VSS
(exposed pad)
IO Pads
Core Logic &
PHY digital
Internal 1.2 V Core
+3.3 V ^Regulator +1.2 V
(IN)
(OUT)
enable
Internal 1.2 V Oscillator
+3.3 V ^Regulator +1.2 V
(IN)
(OUT)
enable _VSS
Crystal Oscillator
VSS
Ethernet PHY 1
Analog
Ethernet Master
Bias
Ethernet PHY 2
Analog
PLL
+1.2 V
VDDCR
VDDCR
VDDCR
(Pin 6)
OSCVDD12
OSCVSS
VDD12TX1
VDD12TX2
Note: Bypass and bulk caps as needed for PCB
 2015 Microchip Technology Inc.
DS00001925A-page 39