LAN9353 Datasheet, PDF (85/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
(IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin de-
asserts, regardless of the reason.
FIGURE 8-1:
FUNCTIONAL INTERRUPT HIERARCHY
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
Bit 29 (1588_EVNT)
of INT_STS register
1588 Time Stamp Interrupt Registers
1588_INT_STS
1588_INT_EN
Bit 28 (SWITCH_INT)
of INT_STS register
Switch Fabric Interrupt Registers
SW_IMR
SW_IPR
Bit 6 (BM)
of SW_IPR register
Buffer Manager Interrupt Registers
BM_IMR
BM_IPR
Bit 5 (SWE)
of SW_IPR register
Switch Engine Interrupt Registers
SWE_IMR
SWE_IPR
Bits [2,1,0] (MAC_[2,1,0])
of SW_IPR register
Port [2,1,0] MAC Interrupt Registers
MAC_IMR_[2,1,0]
MAC_IPR_[2,1,0]
Bit 27 (PHY_INT_B)
of INT_STS register
PHY B Interrupt Registers
PHY_INTERRUPT_SOURCE_B
PHY_INTERRUPT_MASK_B
Bit 26 (PHY_INT_A)
of INT_STS register
PHY A Interrupt Registers
PHY_INTERRUPT_SOURCE_A
PHY_INTERRUPT_MASK_A
Bit 17 (PME_INT)
of INT_STS register
Power Management Control Register
PMT_CTRL
Bit 12 (GPIO)
of INT_STS register
GPIO Interrupt Register
GPIO_INT_STS_EN
 2015 Microchip Technology Inc.
DS00001925A-page 85