LAN9353 Datasheet, PDF (368/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.4.2 MII INTERFACE TIMING (PHY MODE)
This section specifies the MII interface input and output timing when in PHY mode.
FIGURE 13-3:
MII OUTPUT TIMING (PHY MODE)
Px_OUTCLK
(output)
t_clkp
t_clkh t_clkl
t_val
t_val
t_hold
Px_OUTD[3:0]
t_hold
t_val
Px_OUTDV
TABLE 13-3: MII OUTPUT TIMING VALUES (PHY MODE)
Symbol
t_clkp
t_clkh
t_clkl
t_val
t_hold
Description
Px_OUTCLK period
Px_OUTCLK high time
Px_OUTCLK low time
Px_OUTD[3:0], Px_OUTDV output valid from ris-
ing edge of Px_OUTCLK
Px_OUTD[3:0], Px_OUTDV output hold from ris-
ing edge of Px_OUTCLK
Min
40
t_clkp * 0.4
t_clkp * 0.4
-
10.0
Max
-
t_clkp * 0.6
t_clkp * 0.6
28.0
-
Units
ns
ns
ns
ns
ns
Note 3: Timing was designed for system load between 10 pF and 25 pF.
Notes
Note 3
Note 3
DS00001925A-page 368
 2015 Microchip Technology Inc.