LAN9353 Datasheet, PDF (204/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
packet will be loaded into the pause counter. The pause function is enabled by either Auto-Negotiation or manually as
discussed in Section 10.5.1, "Flow Control Enable Logic," on page 226. Pause frames are consumed by the MAC and
are not sent to the Switch Engine. Non-pause control frames are optionally filtered or forwarded.
Note: To meet the IEEE 802.1 Filtering Database requirements, the MAC address of 01-80-C2-00-00-01 should
be added into the ALR address table as filtering entries by either EEPROM sequence or by software.
When the receive FIFO is full and additional data continues to be received, an overrun condition occurs and the frame
is discarded (FIFO space recovered) or marked as a bad frame.
The receive MAC can be disabled from receiving all frames by clearing the RX Enable (RXEN) bit of the Port x MAC
Receive Configuration Register (MAC_RX_CFG_x).
For information on MAC EEE functionality, refer to Section 10.2.3, "IEEE 802.3az Energy Efficient Ethernet," on
page 205.
10.2.1.1 Receive Counters
The receive MAC gathers statistics on each packet and increments the related counter registers. The following receive
counters are supported for each Switch Fabric port. Refer to Table 10-9, “Indirectly Accessible Switch Control and Status
Registers,” on page 246 and Section 10.7.2.3 through Section 10.7.2.22 for detailed descriptions of these counters.
• Total undersized packets (Section 10.7.2.3, on page 261)
• Total packets 64 bytes in size (Section 10.7.2.4, on page 261)
• Total packets 65 through 127 bytes in size (Section 10.7.2.5, on page 262)
• Total packets 128 through 255 bytes in size (Section 10.7.2.6, on page 262)
• Total packets 256 through 511 bytes in size (Section 10.7.2.7, on page 263)
• Total packets 512 through 1023 bytes in size (Section 10.7.2.8, on page 263)
• Total packets 1024 through maximum bytes in size (Section 10.7.2.9, on page 264)
• Total oversized packets (Section 10.7.2.10, on page 264)
• Total OK packets (Section 10.7.2.11, on page 265)
• Total packets with CRC errors (Section 10.7.2.12, on page 265)
• Total multicast packets (Section 10.7.2.13, on page 266)
• Total broadcast packets (Section 10.7.2.14, on page 266)
• Total MAC Pause packets (Section 10.7.2.15, on page 267)
• Total fragment packets (Section 10.7.2.16, on page 267)
• Total jabber packets (Section 10.7.2.17, on page 268)
• Total alignment errors (Section 10.7.2.18, on page 268)
• Total bytes received from all packets (Section 10.7.2.19, on page 269)
• Total bytes received from good packets (Section 10.7.2.20, on page 269)
• Total packets with a symbol error (Section 10.7.2.21, on page 270)
• Total MAC control packets (Section 10.7.2.22, on page 270)
• Total number of RX LPIs received (Section 10.7.2.23, on page 271)
• Total time in RX LPI state (Section 10.7.2.24, on page 271)
10.2.2 TRANSMIT MAC
The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the preamble and
SFD, calculating and appending the frame checksum value, optionally padding undersize packets to meet the minimum
packet requirement size (64 bytes) and maintaining a standard inter-frame gap time during transmit.
The transmit MAC can operate at 10/100Mbps, half or full-duplex and with or without flow control depending on the state
of the transmission. In half-duplex mode, the transmit MAC meets CSMA/CD IEEE 802.3 requirements. The transmit
MAC will re-transmit if collisions occur during the first 64 bytes (normal collisions) or will discard the packet if collisions
occur after the first 64 bytes (late collisions). The transmit MAC follows the standard truncated binary exponential back-
off algorithm, collision and jamming procedures.
The transmit MAC pre-pends the standard preamble and SFD to every packet from the FIFO. The transmit MAC also
follows, as default, the standard Inter-Frame Gap (IFG). The default IFG is 96 bit times and can be adjusted via the IFG
Config field of the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x).
DS00001925A-page 204
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