LAN9353 Datasheet, PDF (406/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
• If enabled via the TX PTP Domain Match Enable (TX_PTP_DOMAIN_EN) bit in the 1588 Port x TX Timestamp
Configuration Register (1588_TX_TIMESTAMP_CONFIG_x), the domainNumber field of the PTP header is
checked against the TX PTP Domain (TX_PTP_DOMAIN[7:0]) value in the same register. Only those messages
with a matching domain will be have their egress times saved.
• If enabled via the TX PTP Alternate Master Enable (TX_PTP_ALT_MASTER_EN) bit in the 1588 Port x TX Time-
stamp Configuration Register (1588_TX_TIMESTAMP_CONFIG_x), the alternateMasterFlag in the flagField of
the PTP header is checked and only those messages with an alternateMasterFlag set to 0 will be have their
egress times saved.
At the end of the frame, the frame’s FCS and the UDP checksum (for IPv4 and IPv6 formats) are verified. FCS checking
can be disabled using the TX PTP FCS Check Disable (TX_PTP_FCS_DIS) bit in the 1588 Port x TX Timestamp Con-
figuration Register (1588_TX_TIMESTAMP_CONFIG_x). UDP checksum checking can be disabled using the TX PTP
UDP Checksum Check Disable (TX_PTP_UDP_CHKSUM_DIS) bit in the same register.
Note: A IPv4 UDP checksum value of 0x0000 indicates that the checksum is not included and is considered a
pass. A IPv6 UDP checksum value of 0x0000 is invalid and is considered a fail.
Note: For IPv6, the UDP checksum calculation includes the IPv6 Pseudo header. Part of the IPv6 Pseudo header
is the final IPv6 destination address.
If the IPv6 packet does not contain a Routing header, then the final IPv6 destination address is the destina-
tion address contained in the IPv6 header.
If the IPv6 packet does contain a Routing header, then the final IPv6 destination address is the address in
the last element of the Routing header.
Note: The UDP checksum is calculated over the entire UDP payload as indicated by the UDP length field and not
the assumed PTP packet length.
Note: The UDP checksum calculation does not included layer 2 pad bytes, if any.
If the FCS and checksum tests pass:
• The latency adjusted, 1588 Clock value, saved above at the start of the frame, is recorded into the 1588 Port x TX
Egress Time Seconds Register (1588_TX_EGRESS_SEC_x) and 1588 Port x TX Egress Time NanoSeconds
Register (1588_TX_EGRESS_NS_x).
• The messageType and sequenceId fields and 12-bit CRC of the portIdentity field of the PTP header are recorded
into the Message Type (MSG_TYPE), Sequence ID (SEQ_ID) and Source Port Identity CRC (SRC_PRT_CRC)
fields of the 1588 Port x TX Message Header Register (1588_TX_MSG_HEADER_x).
The 12-bit CRC of the portIdentity field is created by using the polynomial of X¹² + X¹¹ + X³ + X² + X + 1.
• The corresponding maskable 1588 TX Timestamp Interrupt (1588_TX_TS_INT[2:0]) is set in the 1588 Interrupt
Status Register (1588_INT_STS).
Up to four transmit events are saved per port with the count shown in the 1588 TX Timestamp Count (1588_TX-
_TS_CNT[2:0]) field in the 1588 Port x Capture Information Register (1588_CAP_INFO_x). Additional events are not
recorded. When the appropriate 1588 TX Timestamp Interrupt (1588_TX_TS_INT[2:0]) bit is written as a one to clear,
1588 TX Timestamp Count (1588_TX_TS_CNT[2:0]) will decrement. If there are remaining events, the capture registers
will update to the next event and the interrupt will set again.
TIME STAMPS FROM FORWARDED PACKETS
The transmitter will also save egress times for frames that are forwarded from another port. Typically, these are of no
use to the Host S/W and would need to be discarded. Since these messages also typically have their correction field
adjusted for residence time, they can be distinguished from messages from the Host.
If EGRESS CORRECTION FIELD RESIDENCE TIME ADJUSTMENT, below, is performed on a message, egress times
are not saved if the TX PTP Suppress Timestamps when Correction Field Adjusted (TX_PTP_SUPP_CF_TS) bit in the
1588 Port x TX Modification Register (1588_TX_MOD_x) is set.
DELAY_REQ EGRESS TIME SAVING
Normally, in ordinary clock operation, the egress time of transmitted Delay_Req packets are saved and read by the Host
S/W. To avoid the need to read these timestamps via register access, the egress time of the last transmitted Delay_Req
packet on the port can be inserted into Delay_Resp packets received on the port.
DS00001925A-page 406
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