LAN9353 Datasheet, PDF (166/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Index (In Decimal): 3.32805
Size:
16 bits
Bits
Description
15:0 Wakeup Filter Byte Mask [63:48]
Index (In Decimal): 3.32806
Size:
Type
R/W/
NASR
Note 29
Default
0000h
16 bits
Bits
Description
15:0 Wakeup Filter Byte Mask [47:32]
Index (In Decimal): 3.32807
Size:
Type
R/W/
NASR
Note 29
Default
0000h
16 bits
Bits
Description
15:0 Wakeup Filter Byte Mask [31:16]
Index (In Decimal): 3.32808
Size:
Type
R/W/
NASR
Note 29
Default
0000h
16 bits
Bits
Description
15:0 Wakeup Filter Byte Mask [15:0]
Type
R/W/
NASR
Note 29
Default
0000h
Note 29: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
DS00001925A-page 166
 2015 Microchip Technology Inc.