LAN9353 Datasheet, PDF (258/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.1.4 Switch Global Interrupt Pending Register (SW_IPR)
Register #:
0005h
Size:
32 bits
This read-only register contains the pending global interrupts for the Switch Fabric. A set bit indicates an unmasked bit
in the corresponding Switch Fabric sub-system has been triggered. All switch-related interrupts in this register may be
masked via the Switch Global Interrupt Mask Register (SW_IMR). When an unmasked Switch Fabric interrupt is gen-
erated in this register, the interrupt will trigger the Switch Fabric Interrupt Event (SWITCH_INT) bit in the Interrupt Status
Register (INT_STS). Refer to Section 8.0, "System Interrupts," on page 84 for more information.
Bits
Description
31:7 RESERVED
6
Buffer Manager Interrupt (BM)
Set when any unmasked bit in the Buffer Manager Interrupt Pending Register
(BM_IPR) is triggered. A read of this register clears this bit.
5
Switch Engine Interrupt (SWE)
Set when any unmasked bit in the Switch Engine Interrupt Pending Register
(SWE_IPR) is triggered. A read of this register clears this bit.
4:3 RESERVED
2
Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see Section
10.7.2.50, on page 285) is triggered. A read of this register clears this bit.
1
Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see Section
10.7.2.50, on page 285) is triggered. A read of this register clears this bit.
0
Port 0 MAC Interrupt (MAC_0)
Set when any unmasked bit in the MAC_IPR_0 register (see Section
10.7.2.50, on page 285) is triggered. A read of this register clears this bit.
Type
RO
RC
RC
RO
RC
RC
RC
Default
-
0b
0b
-
0b
0b
0b
DS00001925A-page 258
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