LAN9353 Datasheet, PDF (194/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.5 Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x)
Offset:
PORT0: 1D0h
PORT1: 0D0h
Index (decimal): 4
Size:
32 bits
16 bits
This read/write register contains the advertised ability of the Virtual PHY and is used in the Auto-Negotiation process
with the link partner.
Bits
Description
31:16 RESERVED
(See Note 49)
15 Next Page
This bit determines the advertised next page capability and is always 0.
0: Virtual PHY does not advertise next page capability
1: Virtual PHY advertises next page capability
14 RESERVED
13 Remote Fault
This bit is not used since there is no physical link partner.
12 RESERVED
11 Asymmetric Pause
This bit determines the advertised asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner advertised
1: Asymmetric PAUSE toward link partner advertised
10 Symmetric Pause
This bit determines the advertised symmetric pause capability.
0: No Symmetric PAUSE toward link partner advertised
1: Symmetric PAUSE toward link partner advertised
9
100BASE-T4
This bit determines the advertised 100BASE-T4 capability and is always 0.
0: 100BASE-T4 ability not advertised
1: 100BASE-T4 ability advertised
8
100BASE-X Full Duplex
This bit determines the advertised 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not advertised
1: 100BASE-X full duplex ability advertised
7
100BASE-X Half Duplex
This bit determines the advertised 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not advertised
1: 100BASE-X half duplex ability advertised
Type
RO
RO
RO
RO
RO
R/W
R/W
RO
R/W
R/W
Default
-
0b
Note 50
-
0b
Note 51
-
Note 52
Note 52
0b
Note 53
1b
1b
DS00001925A-page 194
 2015 Microchip Technology Inc.