LAN9353 Datasheet, PDF (302/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.12 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS)
Register #:
1810h
This register indicates the current VLAN command status.
Size:
32 bits
Bits
Description
31:1 RESERVED
0
Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit self-clears once the command has finished.
Type
RO
RO
SC
Default
-
0b
10.7.3.13 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
Register #:
1811h
Size:
32 bits
This register is used to read and write the DIFFSERV table. A write to this address performs the specified access. This
table is used to map the received IP ToS/CS to a priority.
For a read access, the Operation Pending bit in the Switch Engine DIFFSERV Table Command Status Register (SWE_-
DIFFSERV_TBL_CMD_STS) indicates when the command is finished. The Switch Engine DIFFSERV Table Read Data
Register (SWE_DIFFSERV_TBL_RD_DATA) can then be read.
For a write access, the Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
should be written first. The Operation Pending bit in the Switch Engine DIFFSERV Table Command Status Register
(SWE_DIFFSERV_TBL_CMD_STS) indicates when the command is finished.
Bits
Description
31:8 RESERVED
7
DIFFSERV Table RnW
This bit specifies a read(1) or a write(0) command.
6
RESERVED
5:0 DIFFSERV Table Index
This field specifies the ToS/CS entry that is accessed.
Type
RO
R/W
RO
R/W
Default
-
0b
-
000000b
DS00001925A-page 302
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