LAN9353 Datasheet, PDF (467/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.38 1588 PORT X TX MODIFICATION REGISTER (1588_TX_MOD_X)
Offset:
Bank:
164h
2
Size:
32 bits
This register is used to configure TX PTP message modifications.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31 TX PTP Clear Four Byte Reserved Field (TX_PTP_CLR_4_RSVRD)
This bit enables the clearing of the four byte reserved field if the frame was
modified on transmission.
30 TX PTP Suppress Timestamps when Correction Field Adjusted
(TX_PTP_SUPP_CF_TS)
This bit prevents egress times from being saved if correction field modifica-
tion is done. This is used to suppress timestamps from frames forwarded
across the switch.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
29 TX PTP Pdelay_Resp Message Turnaround Time Insertion
(TX_PTP_PDRESP_TA_INSERT)
Note:
This bit enables the turnaround time between the received
Pdelay_Req and the transmitted Pdelay_Resp to be inserted into
the correction field of Pdelay_Resp messages sent by the Host.
28 TX PTP Sync Message Egress Time Insertion
(TX_PTP_SYNC_TS_INSERT)
This bit enables the egress time to be inserted into the originTimestamp field
of Sync messages sent by the Host.
27:22
TX PTP 4 Reserved Bytes Offset (TX_PTP_4_RSVD_OFFSET[5:0])
This field specifies the offset into the PTP header of the four reserved bytes
which the transmitter would clear if enabled.
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
21:16
TX PTP 1 Reserved Byte Offset (TX_PTP_1_RSVD_OFFSET[5:0])
This field specifies the offset into the PTP header where the transmitter can
retrieve the seconds portion of the ingress time.
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
Type
R/W
R/W
R/W
R/W
R/W
R/W
Default
0b
0b
0b
0b
010000b
000101b
 2015 Microchip Technology Inc.
DS00001925A-page 467