LAN9353 Datasheet, PDF (57/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
2
Port B PHY Reset (PHY_B_RST)
Setting this bit resets the Port B PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port B PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note: This bit is not accessible via the EEPROM Loader’s register
initialization function (Section 12.4.5).
Type
R/W
SC
1
Port A PHY Reset (PHY_A_RST)
R/W
Setting this bit resets the Port A PHY. The internal logic automatically holds
SC
the PHY reset for a minimum of 102uS. When the Port A PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note: This bit is not accessible via the EEPROM Loader’s register
initialization function (Section 12.4.5).
0
Digital Reset (DIGITAL_RST)
R/W
Setting this bit resets the complete chip except the PLL, Virtual PHY 1, Virtual
SC
PHY 0, Port B PHY and Port A PHY. All system CSRs are reset except for
any NASR type bits. Any in progress EEPROM commands (including
RELOAD) are terminated.
The EEPROM Loader will automatically reload the configuration following
this reset, but will not reset Virtual PHY 1, Virtual PHY 0, Port B PHY or Port
A PHY. If desired, the above PHY resets can be issued once the device is
configured.
When the chip is released from reset, this bit is automatically cleared. All
writes to this bit are ignored while this bit is set.
Note: This bit is not accessible via the EEPROM Loader’s register
initialization function (Section 12.4.5).
Default
0b
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 57