LAN9353 Datasheet, PDF (27/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
Buffer
Type
Description
VIS
(PU)
MII MAC Mode: This pin is an input from the exter-
nal PHY and indicates a collision event.
1
Port 0 MII
Collision
P0_COL
VO8
MII PHY Mode: This pin is an output to the external
MAC indicating a collision event. The output driver
is disabled when the Isolate (VPHY_ISO) bit is set
in the Port 0 Port x Virtual PHY Basic Control Regis-
ter (VPHY_BASIC_CTRL_x).
-
RMII MAC and RMII PHY Modes: This pin is not
used.
VIS
(PU)
MII MAC Mode: This pin is an input from the exter-
nal PHY and indicates a network carrier.
1
Port 0 MII
Carrier Sense
P0_CRS
VO8
MII PHY Mode: This pin is an output to the external
MAC indicating a network carrier. The output driver
is disabled when the Isolate (VPHY_ISO) bit is set
in the Port 0 Port x Virtual PHY Basic Control Regis-
ter (VPHY_BASIC_CTRL_x).
-
RMII MAC and RMII PHY Modes: This pin is not
used.
SMI/MII Slave Management Modes: This is the
management data to/from an external master and is
used to access port 0’s Virtual PHY, the two physical
PHYs and internal registers.
Port 0 SMI/MII
1
Management
Data
Input/Output
P0_MDIO
VIS/VO8
MII Master Management Modes: This is the man-
agement data to/from an external PHY(s).
Note:
An external pull-up is required when the
SMI or MII management interface is
used, to ensure that the IDLE state of the
MDIO signal is a logic one.
Note:
An external pull-up is recommended
when the SMI or MII management inter-
face is not used, to avoid a floating sig-
nal.
Port 0 SMI/MII
1 Management
Clock
P0_MDC
SMI/MII Slave Management Modes: This is the
management clock input from an external master
and is used to access port 0’s Virtual PHY, the two
VIS ^{physical PHYs and internal registers.}
Note:
When SMI or MII is not used, an external
pull-down is recommended to avoid a
floating signal.
VO8
MII Master Management Modes: This is the man-
agement clock output to an external PHY(s).
Note 6: A series terminating resistor is recommended for the best PCB signal integrity.
Note 7: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 67
for more information.
Note 8: An external supplemental pull-up may be needed, depending upon the input current loading of the external
MAC/PHY device.
 2015 Microchip Technology Inc.
DS00001925A-page 27