LAN9353 Datasheet, PDF (451/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.25 1588 PORT X RX CORRECTION FIELD MODIFICATION REGISTER (1588_RX_CF_MOD_X)
Offset:
Bank:
164h
1
Size:
32 bits
This register is used to configure RX PTP message correction field modifications.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:16 RESERVED
15:0 RX PTP Correction Field Message Type Enable
(RX_PTP_CF_MSG_EN[15:0])
These bits individually enable correction field modification of their respective
message types. Bit 0 of this field corresponds to a message type value of 0
(Sync), bit 1 to message type value 1 (Delay_Req), etc.
Typically Sync, Delay_Req, PDelay_Req and PDelay_Resp messages are
enabled
Type
RO
R/W
Default
-
000Fh
 2015 Microchip Technology Inc.
DS00001925A-page 451