LAN9353 Datasheet, PDF (112/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
F6 = CRC[09] ^ F5 ^ Data[6]
F7 = CRC[08] ^ F6 ^ Data[7]
The CRC-32 is updated as follows:
CRC[15] = CRC[7] ^ F7
CRC[14] = CRC[6]
CRC[13] = CRC[5]
CRC[12] = CRC[4]
CRC[11] = CRC[3]
CRC[10] = CRC[2]
CRC[9] = CRC[1] ^ F0
CRC[8] = CRC[0] ^ F1
CRC[7] = F0 ^ F2
CRC[6] = F1 ^ F3
CRC[5] = F2 ^ F4
CRC[4] = F3 ^ F5
CRC[3] = F4 ^ F6
CRC[2] = F5 ^ F7
CRC[1] = F6
CRC[0] = F7
3. Determine the offset pattern with offset 0 being the first byte of the destination address. Update the offset in the
Filter Pattern Offset field of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x).
Determine Address Matching Conditions:
4. Determine the address matching scheme based on Table 9-5 and update the Filter Broadcast Enable, Filter Any
Multicast Enable, and Address Match Enable bits of the PHY x Wakeup Filter Configuration Register A
(PHY_WUF_CFGA_x) accordingly.
5. If necessary (see step 4), set the desired MAC address to cause the wake event in the PHY x MAC Receive
Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and
PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x).
6. Set the Filter Enable bit of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) to enable
the filter.
Enable Wakeup Frame Detection:
7. Set the Wakeup Frame Enable (WUEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x)
to enable Wakeup Frame detection.
8. Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable
WoL events.
When a match is triggered, the Remote Wakeup Frame Received (WUFR) bit of the PHY x Wakeup Control and Status
Register (PHY_WUCSR_x) will be set. To provide additional visibility to software, the Filter Triggered bit of the PHY x
Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) will be set.
DS00001925A-page 112
 2015 Microchip Technology Inc.