LAN9353 Datasheet, PDF (377/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
FIGURE 13-12: RMII CLOCK INPUT MODE TIMING (PHY MODE)
Px_OUTCLK
(input)
t_clkp
t_clkh t_clkl
t_val
t_val
Px_OUTD[1:0]
t_ohold
Px_OUTDV
Px_IND[1:0],
Px_INER
t_ihold
Px_INDV
t_su t_ihold
t_su t_ihold
t_ohold
t_val
t_ihold
t_su
TABLE 13-12: RMII CLOCK INPUT MODE TIMING VALUES (PHY MODE)
Symbol
t_clkp
t_clkh
t_clkl
t_oval
t_ohold
t_su
t_ihold
Description
Min
Max
Px_OUTCLK period
Px_OUTCLK high time
Px_OUTCLK low time
Px_OUTD[1:0], Px_OUTDV output valid from ris-
ing edge of Px_OUTCLK
Px_OUTD[1:0], Px_OUTDV output hold from ris-
ing edge of Px_OUTCLK
Px_IND[1:0], Px_INDV setup time to rising edge
of Px_INCLK
Px_IND[1:0], Px_INDV input hold time after ris-
ing edge of Px_INCLK
20
t_clkp * 0.35
t_clkp * 0.35
-
3.0
4.0
1.5
-
t_clkp * 0.65
t_clkp * 0.65
14.0
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
Note 12: Timing was designed for system load between 10 pF and 25 pF.
Notes
Note 12
Note 12
Note 12
Note 12
 2015 Microchip Technology Inc.
DS00001925A-page 377