LAN9353 Datasheet, PDF (20/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
1
Port 0 MII
Input Data 3
P0_IND3
1
Port 0 MII
Input Data 2
P0_IND2
1
Port 0 MII/RMII
Input Data 1
P0_IND1
Buffer
Type
VIS
(PD)
VIS
(PD)
-
VIS
(PD)
VIS
(PD)
-
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
Description
MII MAC Mode: This pin is the receive data 3 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 3 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
RMII MAC and RMII PHY Modes: This pin is not
used.
MII MAC Mode: This pin is the receive data 2 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 2 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
RMII MAC and RMII PHY Modes: This pin is not
used.
MII MAC Mode: This pin is the receive data 1 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 1 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
RMII MAC Mode: This pin is the receive data 1 bit
from the external PHY to the switch.
RMII PHY Mode: This pin is the transmit data 1 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Port 0 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
DS00001925A-page 20
 2015 Microchip Technology Inc.