LAN9353 Datasheet, PDF (185/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5 VIRTUAL PHY REGISTERS
This section details the Virtual PHY System CSRs. These registers provide status and control information similar to that
of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY registers are addressable via the memory
map, as described in Table 5-1, “System Control and Status Registers,” on page 43, as well as serially via the MII man-
agement protocol (IEEE 802.3 clause 22). When accessed serially, these registers are accessed through the MII man-
agement pins (in PHY modes only) via the MII serial management protocol specified in IEEE 802.3 clause 22. See
Section 2.0, "General Description," on page 8 for a detailed description of the various device modes.
When being accessed serially, the Virtual PHY will respond when the PHY address equals the address assigned by the
phy_addr_sel_strap configuration strap, as defined in Section 9.1.1, "PHY Addressing," on page 94. A list of all Virtual
PHY register indexes for serial access can be seen in Table 9-21. For Virtual PHY functionality and operation informa-
tion, see Section 9.3, "Virtual PHYs 0 and 1," on page 181.
Note:
All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All
functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in
decimal) is included under the memory mapped offset of each Virtual PHY register as a reference. For addi-
tional information, refer to the IEEE 802.3 Specification.
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII management
of PHYs.
TABLE 9-21: VIRTUAL PHY MII SERIALLY ADDRESSABLE REGISTER INDEX
ADDRESS
(DIRECT)
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
0C0h
0C4h
0C8h
0CCh
0D0h
0D4h
0D8h
INDEX #
(INDIRECT)
0
1
2
3
4
5
6
31
0
1
2
3
4
5
6
Register Name (SYMBOL)
VPHY 0 Registers
Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) x=0
Port x Virtual PHY Basic Status Register (VPHY_BASIC_STATUS_x) x=0
Port x Virtual PHY Identification MSB Register (VPHY_ID_MSB_x) x=0
Port x Virtual PHY Identification LSB Register (VPHY_ID_LSB_x) x=0
Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x)
x=0
Port x Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY_x) x=0
Port x Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP_x) x=0
Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CON-
TROL_STATUS_x) x=0
VPHY 1 Registers
Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) x=1
Port x Virtual PHY Basic Status Register (VPHY_BASIC_STATUS_x) x=1
Port x Virtual PHY Identification MSB Register (VPHY_ID_MSB_x) x=1
Port x Virtual PHY Identification LSB Register (VPHY_ID_LSB_x) x=1
Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x)
x=1
Port x Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY_x) x=1
Port x Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP_x) x=1
 2015 Microchip Technology Inc.
DS00001925A-page 185