LAN9353 Datasheet, PDF (195/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
6
10BASE-T Full Duplex
This bit determines the advertised 10BASE-T full duplex capability.
Type
R/W
Default
1b
0: 10BASE-T full duplex ability not advertised
1: 10BASE-T full duplex ability advertised
5
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
R/W
1b
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
4:0 Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
R/W
00001b
Note 54
Note 49: The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD bound-
ary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Note 50: The Virtual PHY does not support next page capability. This bit value will always be 0.
Note 51: The Remote Fault bit is not useful since there is no actual link partner to send a fault to.
Note 52: The Symmetric Pause and Asymmetric Pause bits default to 1 if the manual_FC_strap_x configuration strap
is low (both Symmetric and Asymmetric are advertised), and 0 if the manual_FC_strap_x configuration strap
is high.
Note 53: Virtual 100BASE-T4 is not supported.
Note 54: The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this field.
 2015 Microchip Technology Inc.
DS00001925A-page 195