LAN9353 Datasheet, PDF (144/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.16 PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x)
Index (In Decimal): 25
Size:
16 bits
Bits
15
14
13:11
10:9
8
7:0
Description
TDR Enable
0 = TDR mode disabled
1 = TDR mode enabled
Note: This bit self clears when TDR completes
(TDR Channel Status goes high)
TDR Analog to Digital Filter Enable
0 = TDR analog to digital filter disabled
1 = TDR analog to digital filter enabled (reduces noise spikes during
TDR pulses)
RESERVED
TDR Channel Cable Type
Indicates the cable type determined by the TDR test.
00 = Default
01 = Shorted cable condition
10 = Open cable condition
11 = Match cable condition
TDR Channel Status
When high, this bit indicates that the TDR operation has completed. This bit
will stay high until reset or the TDR operation is restarted (TDR Enable = 1)
TDR Channel Length
This eight bit value indicates the TDR channel length during a short or open
cable condition. Refer to Section 9.2.15.1, "Time Domain Reflectometry
(TDR) Cable Diagnostics," on page 114 for additional information on the
usage of this field.
Note:
This field is not valid during a match cable condition. The PHY x
Cable Length Register (PHY_CABLE_LEN_x) must be used to
determine cable length during a non-open/short (match) condition.
Refer to Section 9.2.15, "Cable Diagnostics," on page 113 for
additional information.
Type
R/W
NASR
SC
Note 22
R/W
NASR
Note 22
RO
R/W
NASR
Note 22
R/W
NASR
Note 22
R/W
NASR
Note 22
Default
0b
0b
-
00b
0b
00h
Note 22: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
DS00001925A-page 144
 2015 Microchip Technology Inc.