LAN9353 Datasheet, PDF (213/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.3.3.1 Port Default Priority
As detailed in Figure 10-3, the default priority is based on the ingress port’s priority bits in its port VID value. Separate
values exist for packets with or without a broadcast destination address. The PVID table is read and written by using
the Switch Engine VLAN Command Register (SWE_VLAN_CMD), the Switch Engine VLAN Write Data Register
(SWE_VLAN_WR_DATA), the Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) and the Switch
Engine VLAN Command Status Register (SWE_VLAN_CMD_STS). Refer to Section 10.7.3.9, on page 297 through
Section 10.7.3.12, on page 302 for detailed VLAN register descriptions.
10.3.3.2 IP Precedence Based Priority
The transmit priority queue can be chosen based on the Precedence bits of the IPv4 TOS octet. This is supported for
tagged and non-tagged packets for both type field and length field encapsulations. The Precedence bits are the three
most significant bits of the IPv4 TOS octet.
10.3.3.3 DIFFSERV Based Priority
The transmit priority queue can be chosen based on the DIFFSERV usage of the IPv4 TOS or IPv6 Traffic Class octet.
This is supported for tagged and non-tagged packets for both type field and length field encapsulations.
The DIFFSERV table is used to determine the packet priority from the 6-bit Differentiated Services (DS) field. The DS
field is defined as the six most significant bits of the IPv4 TOS octet or the IPv6 Traffic Class octet and is used as an
index into the DIFFSERV table. The output of the DIFFSERV table is then used as the priority. This priority is then
passed through the Traffic Class table to select the transmit priority queue.
Note: The DIFFSERV table is not initialized upon reset or power-up. If DIFFSERV is enabled, then the full table
must be initialized by the host.
The DIFFSERV table is read and written by using the Switch Engine DIFFSERV Table Command Register (SWE_DIFF-
SERV_TBL_CFG), the Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA), the
Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) and the Switch Engine DIFF-
SERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS). Refer to Section 10.7.3.13, on page 302
through Section 10.7.3.16, on page 303 for detailed DIFFSERV register descriptions.
10.3.3.4 VLAN Priority
As detailed in Figure 10-3, the transmit priority queue can be taken from the priority field of the VLAN tag. The VLAN
priority is sent through a per port Priority Regeneration table, which is used to map the VLAN priority into a user defined
priority.
The Priority Regeneration table is programmed by using the Switch Engine Port 0 Ingress VLAN Priority Regeneration
Table Register (SWE_INGRSS_REGEN_TBL_0), the Switch Engine Port 1 Ingress VLAN Priority Regeneration Table
Register (SWE_INGRSS_REGEN_TBL_1) and the Switch Engine Port 2 Ingress VLAN Priority Regeneration Table
Register (SWE_INGRSS_REGEN_TBL_2). Refer to Section 10.7.3.34, on page 317 through Section 10.7.3.36, on
page 319 for detailed descriptions of these registers.
10.3.4 VLAN SUPPORT
The Switch Engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16 active VLAN
entries, each consisting of the VID, the port membership and un-tagging instructions.
FIGURE 10-4:
VLAN TABLE ENTRY STRUCTURE
17
16
15
14
13
12 11
...
0
Member
Port 2
Un-tag
Port 2
Member
Port 1
Un-tag
Port 1
Member
MII
Un-tag
MII
VID
 2015 Microchip Technology Inc.
DS00001925A-page 213