LAN9353 Datasheet, PDF (108/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.10 PHY POWER-DOWN MODES
There are two PHY power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. These
modes are described in the following subsections.
Note: For more information on the various power management features of the device, refer to Section 6.3,
"Power Management," on page 58.
The power-down modes of each PHY are controlled independently.
The PHY power-down modes do not reload or reset the PHY registers.
9.2.10.1 General Power-Down
This power-down mode is controlled by the Power Down (PHY_PWR_DWN) bit of the PHY x Basic Control Register
(PHY_BASIC_CONTROL_x). In this mode the entire transceiver, except the PHY management control interface, is
powered down. The transceiver will remain in this power-down state as long as the Power Down (PHY_PWR_DWN) bit
is set. When the Power Down (PHY_PWR_DWN) bit is cleared, the transceiver powers up and is automatically reset.
9.2.10.2 Energy Detect Power-Down
This power-down mode is enabled by setting the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode
Control/Status Register (PHY_MODE_CONTROL_STATUS_x). In this mode, when no energy is present on the line, the
entire transceiver is powered down (except for the PHY management control interface, the SQUELCH circuit and the
ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-
T, or Auto-Negotiation signals.
In this mode, when the Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CON-
TROL_STATUS_x) signal is low, the transceiver is powered down and nothing is transmitted. When energy is received,
via link pulses or packets, the Energy On (ENERGYON) bit goes high, and the transceiver powers up. The transceiver
automatically resets itself into the state prior to power-down, and asserts the INT7 bit of the PHY x Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may be
lost.
When the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode Control/Status Register (PHY_MODE_-
CONTROL_STATUS_x) is low, energy detect power-down is disabled.
When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs
in EDPD via the EDPD TX NLP Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register
(PHY_EDPD_CFG_x). When enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer
Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). When in
EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD RX
Single NLP Wake Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CF-
G_x) will enable the device to wake on reception of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared,
the maximum interval for detecting reception of two NLPs to wake from EDPD is configurable via the EDPD RX NLP
Max Interval Detect Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDP-
D_CFG_x).
The energy detect power down feature is part of the broader power management features of the device and can be used
to trigger the power management event or general interrupt request pin (IRQ). This is accomplished by enabling the
energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable
(bit 14 for PHY A, bit 15 for PHY B) of the Power Management Control Register (PMT_CTRL). Refer to Power Manage-
ment for additional information.
9.2.11 ENERGY EFFICIENT ETHERNET
The PHYs support IEEE 802.3az Energy Efficient Ethernet (EEE). The EEE functionality is enabled/disabled via the
PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration
Register (PHY_EDPD_CFG_x). Energy Efficient Ethernet is enabled or disabled by default via the EEE_enable_strap_1
and EEE_enable_strap_2 configuration straps. In order for EEE to be utilized, the following conditions must be met:
• EEE functionality must be enabled via the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the PHY x
EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x)
• The 100BASE-TX EEE bit of the MMD PHY x EEE Advertisement Register (PHY_EEE_ADV_x) must be set
DS00001925A-page 108
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