LAN9353 Datasheet, PDF (59/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
This module also masks the status bits with the corresponding enable bits (Energy-Detect / WoL Enable Port B
(ED_WOL_EN_B) and Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)) and combines the results together to
generate the Power Management Interrupt Event (PME_INT) status bit in the Interrupt Status Register (INT_STS). The
PME_INT status bit is then masked with the Power Management Event Interrupt Enable (PME_INT_EN) bit and com-
bined with the other interrupt sources to drive the IRQ output pin.
Note: The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of
PME_INT_EN.
When the PM_WAKE bit of the Power Management Control Register (PMT_CTRL) is set, the PME event will automat-
ically wake up the system in certain chip level power modes, as described in Section 6.3.4.2, "Exiting Low Power
Modes," on page 61.
FIGURE 6-1:
PME INTERRUPT SIGNAL GENERATION
INT8 (bit 8) of
PHY_INTERRUPT_SOURCE_A register
INT8_MASK (bit 8) of
PHY_INTERRUPT_MASK_A register
INT7 (bit 7) of
PHY_INTERRUPT_SOURCE_A register
INT7_MASK (bit 7) of
PHY_INTERRUPT_MASK_A register
INT8 (bit 8) of
PHY_INTERRUPT_SOURCE_B register
INT8_MASK (bit 8) of
PHY_INTERRUPT_MASK_B register
INT7 (bit 7) of
PHY_INTERRUPT_SOURCE_B register
INT7_MASK (bit 7) of
PHY_INTERRUPT_MASK_B register
Other PHY Interrupts
Other PHY Interrupts
ED_WOL_EN_A (bit
14) of PMT_CTRL
register
ED_WOL_STS_A (bit 16)
of PMT_CTRL register
ED_WOL_EN_B (bit
15) of PMT_CTRL
register
ED_WOL_STS_B (bit 17)
of PMT_CTRL register
Denotes a level-triggered "sticky" status bit
PME_INT (bit 17)
of INT_STS register
Other System
Interrupts
PME_INT_EN (bit 17)
of INT_EN register
IRQ_EN (bit 8)
of IRQ_CFG register
PM_WAKE (bit 28) of
PMT_CTRL register
PME wake-up
Polarity &
Buffer Type
IRQ
Logic
6.3.3 BLOCK LEVEL POWER MANAGEMENT
The device supports software controlled clock disabling of various modules in order to reduce power consumption.
Note:
Disabling individual blocks does not automatically reset the block, it only places it into a static non-opera-
tional state in order to reduce the power consumption of the device. If a block reset is not performed before
re-enabling the block, then care must be taken to ensure that the block is in a state where it can be disabled
and then re-enabled.
6.3.3.1 Disabling The Switch Fabric
The entire Switch Fabric may be disabled by setting the SWITCH_DIS bit in the Power Management Control Register
(PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. A
write of a 0 will reset the count.
 2015 Microchip Technology Inc.
DS00001925A-page 59