LAN9353 Datasheet, PDF (202/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Note 66: The default value of this field is determined via the turbo_mii_enable_strap_0 configuration strap. Refer to
Section 7.2, "Hard-Straps," on page 78 for additional information.
Note 67: The default value of this field is determined via the P0_rmii_clock_dir_strap or P1_rmii_clock_dir_strap con-
figuration strap. Refer to Section 7.2, "Hard-Straps," on page 78 for additional information.
Note 68: The default value of this field is determined via the P0_clock_strength_strap or P1_clock_strength_strap
configuration strap. Refer to Section 7.2, "Hard-Straps," on page 78 for additional information.
Note 69: The default value of this field is the result of the Auto-Negotiation process if the Auto-Negotiation
(VPHY_AN) bit of the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) is set. Otherwise,
this field reflects the Speed Select LSB (VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bit
settings of the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x). Refer to Section 9.3.1,
"Virtual PHY Auto-Negotiation," on page 181 for information on the Auto-Negotiation determination process
of the Virtual PHY.
Note 70: Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset Control
Register (RESET_CTL). The NASR designation is only applicable when the Reset (VPHY_RST) bit of the
Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) is set.
Note 71: The default value of this field is determined via the SQE_test_disable_strap_0 configuration strap. Refer to
Section 7.1, "Soft-Straps," on page 67 for additional information.
DS00001925A-page 202
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