LAN9353 Datasheet, PDF (149/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.20 PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
Index (decimal): 29
Size:
16 bits
This read-only register is used to determine to source of various PHY interrupts. All interrupt source bits in this register
are read-only and latch high upon detection of the corresponding interrupt (if enabled). A read of this register clears the
interrupts. These interrupts are enabled or masked via the PHY x Interrupt Mask Register (PHY_INTER-
RUPT_MASK_x).
Bits
Description
15:9 RESERVED
9
INT9
This interrupt source bit indicates a Link Up (link status asserted).
0: Not source of interrupt
1: Link Up (link status asserted)
8
INT8
0: Not source of interrupt
1: Wake on LAN (WoL) event detected
7
INT7
This interrupt source bit indicates when the Energy On (ENERGYON) bit of
the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STA-
TUS_x) has been set.
0: Not source of interrupt
1: ENERGYON generated
6
INT6
This interrupt source bit indicates Auto-Negotiation is complete.
0: Not source of interrupt
1: Auto-Negotiation complete
5
INT5
This interrupt source bit indicates a remote fault has been detected.
0: Not source of interrupt
1: Remote fault detected
4
INT4
This interrupt source bit indicates a Link Down (link status negated).
0: Not source of interrupt
1: Link Down (link status negated)
3
INT3
This interrupt source bit indicates an Auto-Negotiation LP acknowledge.
0: Not source of interrupt
1: Auto-Negotiation LP acknowledge
Type
RO
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
Default
-
0b
0b
0b
0b
0b
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 149