LAN9353 Datasheet, PDF (129/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.5 PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
Index (decimal): 4
Size:
16 bits
This read/write register contains the advertised ability of the PHY and is used in the Auto-Negotiation process with the
link partner.
Bits
Description
Type
15 Next Page
R/W
0 = No next page ability
1 = Next page capable
14 RESERVED
RO
13 Remote Fault
R/W
This bit determines if remote fault indication will be advertised to the link part-
ner.
0: Remote fault indication not advertised
1: Remote fault indication advertised
12 Extended Next Page
R/W
Note: This bit should be written as 0.
11 Asymmetric Pause
R/W
This bit determines the advertised asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner advertised
1: Asymmetric PAUSE toward link partner advertised
10 Symmetric Pause
R/W
This bit determines the advertised symmetric pause capability.
0: No Symmetric PAUSE toward link partner advertised
1: Symmetric PAUSE toward link partner advertised
9
RESERVED
RO
8
100BASE-X Full Duplex
R/W
This bit determines the advertised 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not advertised
1: 100BASE-X full duplex ability advertised
7
100BASE-X Half Duplex
R/W
This bit determines the advertised 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not advertised
1: 100BASE-X half duplex ability advertised
6
10BASE-T Full Duplex
R/W
This bit determines the advertised 10BASE-T full duplex capability.
0: 10BASE-T full duplex ability not advertised
1: 10BASE-T full duplex ability advertised
Default
0b
-
0b
0b
Note 11
Note 11
-
1b
1b
Note 12
Table 9-14
 2015 Microchip Technology Inc.
DS00001925A-page 129