LAN9353 Datasheet, PDF (260/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
Register #:
Port0: 0401h
Port1: 0801h
Port2: 0C01h
Size:
32 bits
This read/write register configures the packet type passing parameters of the port.
Bits
Description
31:8 RESERVED
7
RESERVED
Note: This bit must always be written as 0.
6
RESERVED
5
Enable Receive Own Transmit
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in half-duplex PHY loop-
back.
4
RESERVED
3
Jumbo2K
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
2
RESERVED
1
Reject MAC Types
When set, MAC control frames (packets with a type field of 8808h) are fil-
tered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
0
RX Enable (RXEN)
When set, the receive port is enabled. When cleared, the receive port is dis-
abled.
Type
RO
R/W
RO
R/W
RO
R/W
RO
R/W
R/W
Default
-
0b
-
0b
-
0b
-
1b
1b
DS00001925A-page 260
 2015 Microchip Technology Inc.