LAN9353 Datasheet, PDF (136/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.10 PHY x MMD Access Control Register (PHY_MMD_ACCESS)
Index (In Decimal): 13
Size:
16 bits
This register in conjunction with the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) provides
indirect access to the MDIO Manageable Device (MMD) registers. Refer to the MDIO Manageable Device (MMD) Reg-
isters on page 154 for additional details.
Bits
Description
15:14 MMD Function
This field is used to select the desired MMD function:
00 = Address
01 = Data, no post increment
10 = RESERVED
11 = RESERVED
13:5 RESERVED
4:0 MMD Device Address (DEVAD)
This field is used to select the desired MMD device address.
(3 = PCS, 7 = auto-negotiation)
Type
R/W
Default
00b
RO
-
R/W
0h
DS00001925A-page 136
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