English
Language : 

LAN9353 Datasheet, PDF (190/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII
LAN9353
Bits
Description
8
Extended Status
This bit displays whether extended status information is in register 15 (per
IEEE 802.3 clause 22.2.4).
Type
RO
Default
0b
Note 41
0: No extended status information in Register 15
1: Extended status information in Register 15
7
RESERVED
RO
-
6
MF Preamble Suppression
RO
0b
This bit indicates whether the Virtual PHY accepts management frames with
the preamble suppressed.
0: Management frames with preamble suppressed not accepted
1: Management frames with preamble suppressed accepted
5
Auto-Negotiation Complete
This bit indicates the status of the Auto-Negotiation process.
0: Auto-Negotiation process not completed
1: Auto-Negotiation process completed
4
Remote Fault
This bit indicates if a remote fault condition has been detected.
0: No remote fault condition detected
1: Remote fault condition detected
3
Auto-Negotiation Ability
This bit indicates the status of the Virtual PHY’s Auto-Negotiation.
RO
1b
Note 42
RO
0b
Note 43
RO
1b
0: Virtual PHY is unable to perform Auto-Negotiation
1: Virtual PHY is able to perform Auto-Negotiation
2
Link Status
This bit indicates the status of the link.
0: Link is down
1: Link is up
1
Jabber Detect
This bit indicates the status of the jabber condition.
0: No jabber condition detected
1: Jabber condition detected
0
Extended Capability
This bit indicates whether extended register capability is supported.
0: Basic register set capabilities only
1: Extended register set capabilities
RO
1b
Note 43
RO
0b
Note 43
RO
1b
Note 44
Note 39: The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD bound-
ary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Note 40: The Virtual PHY supports 100BASE-X (half and full duplex) and 10BASE-T (half and full duplex) only. All
other modes will always return as 0 (unable to perform).
Note 41: The Virtual PHY does not support Register 15 or 1000 Mb/s operation. Thus this bit is always returned as 0.
Note 42: The Auto-Negotiation Complete bit is first cleared on a reset, but set shortly after (when the Auto-Negotiation
process is run). Refer to Section 9.3.1, "Virtual PHY Auto-Negotiation," on page 181 for additional details.
DS00001925A-page 190
 2015 Microchip Technology Inc.