LAN9353 Datasheet, PDF (384/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.3.5 PHY MANAGEMENT INTERFACE (PMI) REGISTERS
The directly addressable PMI registers are used to indirectly access the Physical PHY registers. Refer to Section 9.2.20,
"Physical PHY Registers," on page 120 for additional information on the PHY registers.
TABLE 14-5: PMI REGISTERS
ADDRESS
0A4h
0A8h
Register Name (SYMBOL)
PHY Management Interface Data Register (PMI_DATA)
PHY Management Interface Access Register (PMI_ACCESS)
14.3.5.1 PHY Management Interface Data Register (PMI_DATA)
Offset:
0A4h
Size:
32 bits
This register is used in conjunction with the PHY Management Interface Access Register (PMI_ACCESS) to perform
read and write operations to the PHYs.
Bits
31:16
15:0
Description
RESERVED
MII Data
This field contains the value read from or written to the PHYs. For a write
operation, this register should be first written with the desired data. For a read
operation, the PMI_ACCESS register is first written and once the command
is finished, this register will contain the return data.
Note:
Upon a read, the value returned depends on the MII Write bit
(MIIWnR) in the PHY Management Interface Access Register
(PMI_ACCESS). If MIIWnR is 0, the data is from the PHY. If
MIIWnR is 1, the data is the value that was last written into this
register.
Note: The EEPROM Loader can only perform register write operations.
Type
RO
R/W
Default
-
0000h
DS00001925A-page 384
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