LAN9353 Datasheet, PDF (43/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
5.1 System Control and Status Registers
The System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 2F8h.
These registers are accessed through the I²C serial interface or the MIIM/SMI serial interface. For more information on
the various device modes and their corresponding address configurations, see Section 2.0, "General Description," on
page 8.
Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their default
value on the assertion of a chip-level reset.
The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the cor-
responding chapter and contains the System CSR descriptions of the associated registers. The register descriptions
are categorized as follows:
• Section 6.2.3, "Reset Registers," on page 56
• Section 6.3.5, "Power Management Registers," on page 62
• Section 8.3, "Interrupt Registers," on page 88
• Section 17.4, "GPIO/LED Registers," on page 489
• Section 12.5, "I2C Master EEPROM Controller Registers," on page 356
• Section 15.8, "1588 Registers," on page 415
• Section 10.6, "Switch Fabric Interface Logic Registers," on page 231
• Section 14.3.5, "PHY Management Interface (PMI) Registers," on page 384
• Section 9.3.5, "Virtual PHY Registers," on page 185
• Section 18.1, "Miscellaneous System Configuration & Status Registers," on page 495
Note: Unlisted registers are reserved for future use.
TABLE 5-1: SYSTEM CONTROL AND STATUS REGISTERS
Address
050h
054h
058h
05Ch
064h
074h
084h
08Ch
090h
09Ch
0A4h
0A8h
0C0h
0C4h
0C8h
0CCh
0D0h
0D4h
0D8h
0DCh
Register Name (Symbol)
Chip ID and Revision (ID_REV)
Interrupt Configuration Register (IRQ_CFG)
Interrupt Status Register (INT_STS)
Interrupt Enable Register (INT_EN)
Byte Order Test Register (BYTE_TEST)
Hardware Configuration Register (HW_CFG)
Power Management Control Register (PMT_CTRL)
General Purpose Timer Configuration Register (GPT_CFG)
General Purpose Timer Count Register (GPT_CNT)
Free Running 25MHz Counter Register (FREE_RUN)
PHY Management Interface Data Register (PMI_DATA)
PHY Management Interface Access Register (PMI_ACCESS)
Virtual PHY 1 Registers
Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) x=1
Port x Virtual PHY Basic Status Register (VPHY_BASIC_STATUS_x) x=1
Port x Virtual PHY Identification MSB Register (VPHY_ID_MSB_x) x=1
Port x Virtual PHY Identification LSB Register (VPHY_ID_LSB_x) x=1
Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x) x=1
Port x Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY_x) x=1
Port x Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP_x) x=1
Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) x=1
1588 Registers
 2015 Microchip Technology Inc.
DS00001925A-page 43