LAN9353 Datasheet, PDF (363/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.1.4.2 Reference Clock Selection
The 50 MHz RMII reference clock can be selected from either the P0_REFCLK pin input or the internal 50 MHz clock.
The choice is based on the setting of the RMII Clock Direction bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x). A low selects P0_REFCLK and a high selects the internal 50 MHz
clock. The high setting also enables P0_REFCLK as an output to be used as the reference clock to the MAC.
13.1.4.3 Clock Drive Strength
When P0_REFCLK is configured as an output via the RMII Clock Direction bit of the Port x Virtual PHY Special Control/
Status Register (VPHY_SPECIAL_CONTROL_STATUS_x), its drive strength is based on the setting of the RMII/Turbo
MII Clock Strength bit of the Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects 12 mA, a high selects 16 mA.
13.1.4.4 Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The SQEOFF bit of the Port x Virtual
PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) has no effect when operating in RMII
PHY mode.
13.1.4.5 Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The Collision Test
(VPHY_COL_TEST) bit of the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) has no effect on sys-
tem operation in RMII PHY mode.
Switch Fabric collision testing is available and is enabled when the Switch Collision Test bit of the Port x Virtual PHY
Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) is set. In this test mode, any transmissions
from the Switch Fabric will result in the assertion of an internal collision signal to the Switch Fabric Port 0. Switch Fabric
collision test occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
13.1.4.6 Loopback Mode
Two forms of loopback testing are available: External MAC loopback and Switch Fabric loopback.
External MAC loopback is enabled when the Loopback (VPHY_LOOPBACK) bit of the Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x) is set. Transmissions from the external MAC are not sent to the Switch Fabric.
Instead, they are looped back onto the receive path. Transmissions from the Switch Fabric are ignored.
Switch Fabric loopback is enabled when the Switch Loopback bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x) is set. Transmissions from the Switch Fabric are not sent to the exter-
nal MAC. Instead, they are looped back internally onto the receive path. Transmissions from the external MAC are
ignored. An internal collision signal to the Switch Fabric is available and is asserted when the Switch Collision Test bit
is set. Switch Fabric loopback occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
13.2 Port 1 Data Path
The MII Data Interface is used to connect the Switch Fabric port to Physical PHY A or the external pins. While connected
to the external pins, it is used to select between PHY and MAC modes and to emulate an RMII PHY or MAC.
13.2.1 PORT 1 INTERNAL PHY MODE
When operating in Internal PHY mode, the Switch Fabric MAC outputs are routed to internal PHY A. Similarly, the Switch
Fabric MAC inputs are sourced from internal PHY A. The duplex of the Switch Fabric MAC is controlled by the PHY.
13.2.2 PORT 1 RMII MAC MODE
When operating in RMII MAC mode, the MII Data Interface mimics the operation of an RMII MAC and is used when
interfacing to an external PHY that does not support the full MII interface. The RMII interface uses a subset of the MII
pins. The P1_OUTD[1:0], P1_OUTDV, P1_IND[1:0], P1_INDV and P1_REFCLK pins are the only MII pins used to com-
municate with the external PHY in this mode.
 2015 Microchip Technology Inc.
DS00001925A-page 363