LAN9353 Datasheet, PDF (288/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
Register #:
1802h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and
contains the last 32 bits of ALR data to be written.
Bits
Description
31:27
26
25
RESERVED
Valid
When set, this bit makes the entry valid. It can be cleared to invalidate a pre-
vious entry that contained the specified MAC address.
Age 1/Override
This bit is used by the aging and forwarding processes.
If the Static bit of this register is cleared, this bit is the msb of the aging timer.
Software should set this bit so that the entry will age in the normal amount of
time.
If the Static bit is set, this bit is used as a port state override bit. When set,
packets received with a destination address that matches the MAC address
in the SWE_ALR_WR_DAT_1 and SWE_ALR_WR_DAT_0 registers will be
forwarded regardless of the port state (except the Disabled state) of the
ingress or egress port(s). This is typically used to allow the reception of
BPDU packets in the non-forwarding state.
24 Static
When this bit is set, this entry will not be removed by the aging process and/
or be changed by the learning process. When this bit is cleared, this entry will
be automatically removed after 5 to 10 minutes of inactivity. Inactivity is
defined as no packets being received with a source address that matches
this MAC address.
Note: This bit is normally set by software when adding manual entries.
23 Age 0/Filter
This bit is used by the aging and forwarding processes.
If the Static bit of this register is cleared, this bit is the lsb of the aging timer.
Software should set this bit so that the entry will age in the normal amount of
time.
22
21:19
If the Static bit is set, this bit is used to filter packets. When set, packets with
a destination address that matches this MAC address will be filtered.
Priority Enable
When set, this bit enables usage of the Priority field for this MAC address
entry. When clear, the Priority field is not used.
Priority
These bits specify the priority that is used for packets with a destination
address that matches this MAC address. This priority is only used if both the
Priority Enable bit of this register and the DA Highest Priority bit of the Switch
Engine Global Ingress Configuration Register (SWE_GLOBAL_IN-
GRSS_CFG) are set.
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0b
0b
000b
DS00001925A-page 288
 2015 Microchip Technology Inc.