LAN9353 Datasheet, PDF(76/523 Page) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

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LAN9353 Datasheet, PDF (76/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

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LAN9353

TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)

Strap Name

EEE_enable_strap_2

EEE_enable_strap_2

(cont.)

Description

Pin / Default Value

Switch Port 2 Energy Efficient Ethernet Enable Strap:

Configures the default value of the Energy Efficient Ethernet

(EEE_ENABLE) bit in the (x=2) Port x MAC Transmit Configu-

ration Register (MAC_TX_CFG_x).

Note:

This has no effect when the PHY is in 100BASE-FX

mode (lack of EEE auto-negotiation results disables

EEE).

Refer to the respective register definition sections for addi-

tional information.

EEEEN

PHY B Energy Efficient Ethernet Enable Strap: This strap

affects the default value of the following register bits (x=B):

EEEEN

â¢ PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit

of the PHY x EDPD NLP / Crossover Time / EEE Configu-

ration Register (PHY_EDPD_CFG_x)

â¢ 100BASE-TX EEE bit of the PHY x EEE Capability Regis-

ter (PHY_EEE_CAP_x)

â¢ 100BASE-TX EEE bit of the PHY x EEE Advertisement

Register (PHY_EEE_ADV_x)

Note: This has no effect when the PHY is in 100BASE-FX

mode.

Refer to the respective register definition sections for addi-

tional information.

SQE_test_disable_strap_0 Port 0 Virtual PHY SQE Heartbeat Disable Strap: Config- 0b

ures the default value of the SQEOFF bit in the (x=0) Port x

Virtual PHY Special Control/Status Register (VPHY_SPE-

CIAL_CONTROL_STATUS_x).

Refer to the respective register definition sections for addi-

tional information.

speed_strap_0

Port 0 Virtual PHY Speed Select Strap: This strap affects

1b

Note: speed_strap_0 and

speed_pol_strap_0 share

the same strap register and

the default value of the following bits in the (x=0) Port x Virtual

PHY Auto-Negotiation Link Partner Base Page Ability Regis-

ter (VPHY_AN_LP_BASE_ABILITY_x):

EEPROM bit.

â¢ 100BASE-X Full Duplex

â¢ 100BASE-X Half Duplex

â¢ 10BASE-T Full Duplex

â¢ 10BASE-T Half Duplex

Refer to Section 9.3.5.6 and Table 9-23 for more information.

This strap also configures the speed for Port 0 when Virtual

Auto-Negotiation fails. Refer to Section 9.2.6.2, "Parallel

Detection," on page 103 for additional information.

Refer to the respective register definition sections for addi-

tional information.

DS00001925A-page 76

ï£ 2015 Microchip Technology Inc.

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