LAN9353 Datasheet, PDF (34/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-10: GPIO, LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)
Num
Pins
Name
LED 3
1
General
Purpose I/O 3
Energy Efficient
Ethernet Enable
Configuration
Strap
LED 2
1
General
Purpose I/O 2
EEPROM Size
Configuration
Strap
Symbol
LED3
GPIO3
EEEEN
LED2
GPIO2
E2PSIZE
Buffer
Type
Description
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 3 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the EEEEN strap value sampled
at reset.
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
This pin is configured to operate as a GPIO when
the LED 3 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
VIS
(PU)
This strap configures the default value of the EEE
Enable 2-1 soft-straps. See Note 12.
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 2 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the E2PSIZE strap value sam-
pled at reset.
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
This pin is configured to operate as a GPIO when
the LED 2 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
This strap configures the value of the EEPROM
size hard-strap. See Note 12.
VIS
(PU)
A low selects 1K bits (128 x 8) through 16K bits (2K
x 8).
A high selects 32K bits (4K x 8) through 512K bits
(64K x 8).
DS00001925A-page 34
 2015 Microchip Technology Inc.