LAN9353 Datasheet, PDF (143/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.15 PHY x TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY_x)
Index (In Decimal): 24
Size:
16 bits
Bits
15
14:12
11:6
5:0
Description
TDR Delay In
0 = Line break time is 2 ms.
1 = The device uses TDR Line Break Counter to increase the line break
time before starting TDR.
TDR Line Break Counter
When TDR Delay In is 1, this field specifies the increase in line break time in
increments of 256 ms, up to 2 seconds.
TDR Pattern High
This field specifies the data pattern sent in TDR mode for the high cycle.
TDR Pattern Low
This field specifies the data pattern sent in TDR mode for the low cycle.
Type
R/W
NASR
Note 21
R/W
NASR
Note 21
R/W
NASR
Note 21
R/W
NASR
Note 21
Default
1b
001b
101110b
011101b
Note 21: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
 2015 Microchip Technology Inc.
DS00001925A-page 143