LAN9353 Datasheet, PDF (362/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.1.3.3 Clock Drive Strength
When operating at 200 Mbps (Turbo mode), the drive strength of P0_INCLK and P0_OUTCLK pins is selected based
on the setting of the RMII/Turbo MII Clock Strength bit of the Port x Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS_x). A low selects 12 mA, a high selects 16 mA. When operating at 10 or
100 Mbps, the drive strength is fixed at 12 mA.
13.1.3.4 Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal, observable on the P0_COL pin, is generated in 10 Mbit half-duplex mode in response
to a transmission from the external MAC. At 0.6 µs to 1.6 µs (1.0 µs nominal) following the de-assertion of P0_INDV,
SQE_HEARTBEAT is set active for 0.5 µs to 1.5 µs (5 to 15 bit times) (1.0 µs nominal). This test is disabled via the
SQEOFF bit of the Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x).
13.1.3.5 Collision Test
Two forms of collision testing are available: External MAC collision testing and Switch Fabric collision testing.
External MAC collision testing is enabled when the Collision Test (VPHY_COL_TEST) bit of the Port x Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL_x) is set. In this test mode, any transmissions from the external MAC will result
in collision signaling to the external MAC via the P0_COL pin.
Switch Fabric collision testing is enabled when the Switch Collision Test bit of the Port x Virtual PHY Special Control/
Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) is set. In this test mode, any transmissions from the Switch
Fabric will result in the assertion of the internal collision signal to the Switch Fabric Port 0. Switch Fabric collision testing
occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
13.1.3.6 Loopback
Two forms of loopback testing are available: External MAC loopback and Switch Fabric loopback.
External MAC loopback is enabled when the Loopback (VPHY_LOOPBACK) bit of the Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x) is set. Transmissions from the external MAC are not sent to the Switch Fabric and
are not used for purposes of signaling data valid, collision or carrier sense to the Switch Fabric. Instead, they are looped
back onto the receive path. Transmissions from the Switch Engine are ignored and are not used for purposes of signal-
ing data valid, collision or carrier sense on the MII pins. The collision output to the external MAC (via P0_COL) is not
generated unless the Collision Test (VPHY_COL_TEST) bit is set. The SQE_HEARTBEAT signal does not drive the
collision output (via P0_COL) during External MAC loopback but can drive it during Switch Fabric loopback. The carrier
sense output on the P0_CRS pin is only based on the transmit enable from the external MAC (via the P0_INDV pin).
Switch Fabric loopback is enabled when the Switch Loopback bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x) is set. Transmissions from the Switch Fabric are not sent to the exter-
nal MAC and are not used for purposes of signaling data valid, collision or carrier sense to the MII pins. Instead, they
are looped back internally onto the receive path. Transmissions from the external MAC are ignored and are not used
for purposes of data valid, collision or carrier sense to the Switch Engine. The collision signal to the Switch Fabric is not
generated unless the Switch Collision Test bit is set. The carrier sense signal is only based on the transmit enable from
the Switch Fabric. Switch Fabric loopback occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
13.1.4 PORT 0 RMII PHY MODE
When operating in RMII PHY mode, the MII Data Interface mimics the operation of an RMII PHY and is used when inter-
facing to an external MAC that does not support the full MII interface. The RMII interface uses a subset of the MII pins.
The P0_OUTD[1:0], P0_OUTDV, P0_IND[1:0], P0_INDV and P0_REFCLK pins are the only MII pins used to commu-
nicate with the external MAC in this mode. This mode provides loopback test capabilities for the Switch Fabric and exter-
nal MAC, as well as collision testing for the Switch Fabric.
Note: The RMII standard does not support collision testing for the external MAC.
13.1.4.1 Isolate
When in RMII PHY mode, if the Isolate (VPHY_ISO) bit of the Port x Virtual PHY Basic Control Register (VPHY_BA-
SIC_CTRL_x) is set, RMII data path output pins are three-stated, the pull-ups and pull-downs are disabled and the RMII
data path input pins are ignored (disabled into the non-active state and powered down). Setting the Isolate (VPHY_ISO)
bit does not cause isolation of the MII management pins and does not affect RMII MAC mode.
DS00001925A-page 362
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