LAN9353 Datasheet, PDF (340/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
11.0 I²C SLAVE CONTROLLER
11.1 Functional Overview
This chapter details the I²C slave controller provided by the device. The I²C slave controller can be used for CPU serial
management and allows CPU access to all system CSRs. The I²C slave controller implements the low level I²C slave
serial interface (start and stop condition detection, data bit transmission/reception and acknowledge generation/recep-
tion), handles the slave command protocol and performs system register reads and writes. The I²C slave controller con-
forms to the NXP I²C-Bus Specification.
11.2 I²C Overview
I²C is a bi-directional 2-wire data protocol. A device that sends data is defined as a transmitter and a device that receives
data is defined as a receiver. The bus is controlled by a master which generates the SCL clock, controls bus access and
generates the start and stop conditions. Either a master or slave may operate as a transmitter or receiver as determined
by the master.
Both the clock (I2CSCL) and data (I2CSDA) signals have digital input filters that reject pulses that are less than 100 ns.
The data pin is driven low when either interface sends a low, emulating the wired-AND function of the I²C bus. Since
the slave interface never drives the clock pin, the wired-AND is not necessary.
The following bus states exist:
• Idle: Both I2CSDA and I2CSCL are high when the bus is idle.
• Start & Stop Conditions: A start condition is defined as a high to low transition on the I2CSDA line while I2CSCL
is high. A stop condition is defined as a low to high transition on the I2CSDA line while I2CSCL is high. The bus is
considered to be busy following a start condition and is considered free 4.7 µs/1.3 µs (for 100 kHz and 400 kHz
operation, respectively) following a stop condition. The bus stays busy following a repeated start condition
(instead of a stop condition). Starts and repeated starts are otherwise functionally equivalent.
• Data Valid: Data is valid, following the start condition, when I2CSDA is stable while I2CSCL is high. Data can only
be changed while the clock is low. There is one valid bit per clock pulse. Every byte must be 8 bits long and is
transmitted MSB first.
• Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth clock pulse for
the acknowledge bit. The transmitter releases I2CSDA (high). The receiver drives I2CSDA low so that it remains
valid during the high period of the clock, taking into account the setup and hold times. The receiver may be the
master or the slave depending on the direction of the data. Typically the receiver acknowledges each byte. If the
master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to
not drive the next byte of data so that the master may generate a stop or repeated start condition.
Figure 11-1 displays the various bus states of a typical I²C cycle.
FIGURE 11-1:
I²C CYCLE
I2CSDA
data
can
change
data
stable
data
can
change
data
can
change
data
stable
data
can
change
S
Sr
P
I2CSCL
Start Condition
Data Valid
or Ack
Re-Start
Condition
Data Valid
or Ack
Stop Condition
DS00001925A-page 340
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